This invention relates to a Time Division Multiplexing(TDM) system, and more particularly, to a transmission/reception concurrent match apparatus for a multiple of TDM channels and a method thereof, wherein, in matching the TDM channels, upon data transmit, a single serial Communication Controller(SCC) stores data to transmit per each data channel into a multiple of First-in First-out buffers(FIFOs) and transmits in order the data from each FIFO by one byte through a TDM bus, and upon data reception, stores the received data through the TDM bus into each FIFO and processes the data from each FIFO by reading out the data in order.
Conventionally, there is serial communication between other boards or systems such as communication between a main processor and a peripheral processor in a control system of a Full Electronic Exchange, in which various protocols are used in the serial communication. One of the protocols is a High Level Data Link Control(HDLC). As illustrated in FIG. 1, a data frame to be exchanged between two systems by the HDLC is consisted of flags, a significant data and a cyclic redundancy code(CRC). The flag shows start and end of the frame and the CRC shows a part that the SCC additionally insert to the frame to test whether frame error has occurred or not. Generally, the CRC utilizes 16 bit or 32 bit. When idle having no significant data, the CRC sequentially transmits logic 1, and if a CPU transfers desired significant data to the SCC, the SCC constructs the data frame and transmits the same other processor. Also, upon data receiving, the SCC finds a flag pattern from a bit stream, senses the start and end of the flag and only transfers the significant data to the CPU.
The TDM bus is a multiple connection bus divided into 32 time slots, in which each time slot correspond to one channel, and the serial communication is executed using the time slots.
In the prior art, to realize the serial communication of multiple channel by the HDLC protocol, it is necessary to connect a multiple of SCC corresponding to each channel, because each time slot has various states of idle, significant and flag.
Therefore, upon matching the TDM channels with the SCCs, respective SCC channel have to be needed per each channel. Accordingly, the SCC must have equal number to the number of the channel for matching each other.
U.S. Pat. No. 5,630,065 discloses a time-division multiplex communication system that matches a plurality of data links and multiplexes them. The system is characterized in that a concentrator processes input signals from the respective data link without affecting the data links and a distributor sends the signals though a common data link from the concentrator to respective individual links according to address information from the address indication channel.
Also, the concentrator has a concentration control function to interconnect the individual links and multiplexes signal over the common data link channel through a an input port switching device and a concentration control device, and the distributor has a distribution control function for distributing link control signals, multiplexed over the common data channel to the individual links based on the address information from the address identification channel through an individual link connecting devices and a distribution control device. As the patent, however, has complex constitution or matching a multiple of links, this system is also noneffective as the above prior art.
It is therefore one object of the present invention to provide, in data transmitting between each system, a transmission concurrent matching apparatus and method for a multiple of TDM channels, in which a signal SCC stores data to transmit per each data channel into a multiple of FIFOs and transmits in order the data from each FIFO by one byte through a TDM bus.
It is therefore other object of the present invention to provide, in data transmitting between each system, a reception concurrent matching apparatus and method for a multiple of TDM channels, in which a signal SCC stores the received data through the TDM bus into each FIFO and processes the data from each FIFO by reading out the data in order.
In accordance with one aspect of the invention, there is provided a transmission concurrent matching apparatus for a multiple of TDM channel for matching data to the transmitted through the channels by the HDLC between respective system such as a main processor and a peripheral processor of a Full Electronic Exchange characterized by: a SCC for producing a plurality of write signals to process sequentially data to transmit per each data channel; a plurality of FIFOs for receiving the write signals form the SCC, storing and outputting the signals according to inputted order thereto; and a control means for reading out in order the data from each FIFO by one byte and outputting a clock, data and a frame synchronous pulse for transmitting into a TDM bus having a multiple of time slots.
In accordance with another aspect of the invention, there is provided a transmission concurrent matching method for a multiple of TDM channels for matching data to be transmitted through the channels by the HDLC between respective system such as a main processor and a peripheral processor of a Full Electronic Exchange characterized by: the steps of: producing a plurality of write signals to process sequentially data to transmit per each data channel; receiving the write signals, storing and outputting the signals according to received order; and reading out in order the data by one byte and outputting a clock, data and a frame synchronous pulse for transmitting into a TDM bus having a multiple of time slots.
In accordance with further aspect of the invention, there is provided a reception concurrent matching apparatus for a multiple of TDM channels for matching data to be received through the channels by the HDLC between respective system such as a main processor and a peripheral processor of a Full Electronic Exchange characterized by: a control means for receiving a clock, data and a frame synchronous pulse from outside system through a TDM bus having a multiple of time slots, and producing a multiple of write signals for data of each time slot; a plurality of FIFOs for storing and outputting according to inputted order thereto the data to be received based on the write signals from the control means; and a SCC for reading out and processing the data from the FIFOs per each time slot.
In accordance still other aspect of the invention, there is provided a reception concurrent matching method for a multiple of TDM channels for matching data to be received through the channels by the HDLC between respective system such as a main processor and a peripheral processor of a Full Electronic Exchange characterized by the steps of: received a clock, data and a frame synchronous pulse from outside system through a TDM bus having a multiple of time slots, and producing a multiple of write signals for data of each time slot; storing and outputting in order the data based on the write signals; and reading out the data per each time slot and processing the data when the data reaches a predetermined level.